Dr. Jay Lewis is a Partner at Microsoft focusing on technology incubation, and on strategic semiconductor supply chain risks. In the tech incubation role, this means ensuring that new ideas have a path to become the next generation of products and customer capabilities. The supply chain role includes addressing critical risks to the continuity and integrity of the hardware supply chain. Prior to starting at Microsoft in 2020 Jay was the Deputy Director of the Microsystems Technology Office at DARPA, and prior to that was a Program Manager at DARPA. He has published over 35 refereed articles and been awarded more than 10 patents.
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist of Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is also currently leading AI/ML and security initiatives at ANSYS. Prior to Apache, he lead a research group on the research of Power/Signal/Thermal Integrity of chipsets based on VLIW architecture at HP Labs. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds twenty patents and has co-authored over 60 technical papers and a popular book on “Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. He is currently in the committee for EDPS, ESDA-EDA and SI2 AI/ML SIG, and an IEEE Senior Member.
Co-Founder and CTO
Dr. Jason Oberg is a co-founder and Chief Technology Officer (CTO) of Cycuity, where he is responsible for overseeing the company’s technology and strategic positioning. Dr. Oberg works closely with Cycuit’s executive management team, engineering teams, and customers to drive the company’s next-generation hardware security products. As a leading expert in hardware security, Dr. Oberg brings years of deep expertise and has facilitated the development of several disruptive hardware security technologies. His work has been cited over 1000 times and he holds seven issued and pending patents. Prior to his CTO role, Dr. Oberg led Cycuity as co-founder and CEO from 2014 – 2020, during which he facilitated raising capital, recruited the initial team, and drove the company’s product revenue growth YoY. He received his B.S. in Computer Engineering from UC Santa Barbara and an M.S. and Ph.D. in Computer Science from UC San Diego.
Senior Security Analyst
Nicole Fern is a Senior Security Analyst at Riscure. She received her PhD degree in Electrical & Computer Engineering from University of California, Santa Barbara in 2016 and continued her research in hardware security as a post-doc before joining industry in 2018. She joined Riscure in 2021 and is currently interested in all things embedded security and hardware hacking!
Principal Embedded Security Engineer
Dan Walters is a Principal Embedded Security Engineer and Group Leader at MITRE Labs in the department for Electronics System Development and Embedded Security. Dan helped to develop MITRE’s Secure Electronics Lab, which has advanced capabilities for researching implementation security issues such as side-channel leakage, fault induction, and trusted hardware. Dan is also a part-time lecturer at the University of Massachusetts-Amherst where he teaches embedded security topics at the graduate level. He received his M.S. in Computer Science with a focus on machine learning for security applications from Tufts University; and his B.S.E. in Computer Engineering, B.S.E. in Electrical Engineering, and B.S.E. in Mathematics from the University of Michigan.
Jeremy Bellay, Ph.D. is a principal investigator in Battelle’s Cyber Trust and Analytics division. He specializes in problems that require the synthesis of complex knowledge structures with sophisticated data driven approaches. Jeremy is particularly interested in an integrative approach to risk and assurance in cyber systems. He led the TAME Forum working group on Hardware Assurance, Weaknesses, Collaboration and Sharing. He is currently an active participant in the SAE G32 Hardware Assurance effort and the ICT SCRM HBOM development working group.
Ujjwal Guin (Member, IEEE) received the Ph.D. degree from the Department of Electrical and Computer Engineering, University of Connecticut, in 2016. He is currently an Assistant Professor with the Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA. He has developed several on-chip structures and techniques to improve the security, trustworthiness, and reliability of integrated circuits. He has authored several journal articles and refereed conference papers. He serves on the organizing committees of HOST, VTS, and PAINE. His current research interests include hardware security and trust, Blockchain, and VLSI design and test. He is a member of the ACM. He has been serving on the technical program committees of several reputed conferences, such as DAC, HOST, VTS, PAINE, VLSID, GLSVLSI, ISVLSI, and Blockchain. He is an active participant in the SAE International G-19A Test Laboratory Standards Development Committee and G-32 Cyber-Physical Systems Security Committee.
Senior Lead Engineer
Booz Allen Hamilton
Saverio Fazzari works for Booz Allen acting as a senior technical advisor to DARPA and other government agencies for numerous programs. His specialty is advanced circuit design and development strategies with a focus on hardware cyber security issues including trusted design and fabrication. Mr. Fazzari’ s experience includes extensive commercial experience, leading production innovation and development across all facets of the electronic design process. Mr. Saverio Fazzari has over 25 years of experience covering the entire electronic product development flow. He has a BSEE from Johns Hopkins, and MSEE from the University of Pittsburgh. He has published over 14 papers in industry journals and technical conferences.
Sohrab Aftabjahani received his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2011. Since 2010, he has been with the Intel Corporation in Oregon contributing to its state-of-art R&D projects in various roles including senior security researcher, senior DFT engineer, senior digital design and validation engineer, and graphics Integration validation engineer. He joined Intel after 9 years of experience working as software and hardware engineer for TRW and Computer Science Corporation, Telecommunications Research Center, and several electronic system design companies. He is a senior IEEE/ACM member and serves as the chair of the IEEE Oregon section computer society and the chair of the Semiconductor Research Corporation (SRC) Trustworthy and Secure Semiconductors and Systems (T3S) Technical Advisory Board (TAB). He has served as a TAB for the SRC T3S and Computer-Aided Design and Test (CADT) since 2014. He was a 2-time recipient of the SRC Mahboob Khan outstanding liaison award in 2016 and 2019.
Beau Bakken is a Principal Engineer at Caspia Technologies leading projects in multiple areas of microelectronic security, including IP protection, fault injection assessment, side-channel analysis, and PCB assurance. He joined Caspia in 2020 and holds a degree in Computer Engineering from the University of Florida.
Mike Borza is a member of the technical staff for Synopsys security IP. He has more than 20 years of experience in security system engineering, and safety critical engineering before that. He is a founder and CTO of Elliptic Technologies, which was acquired by Synopsys. Borza has been an active contributor to the Security Task Group of IEEE 802.1; was an editor of the 802.1AR Secure Device Identifier standard; and is one of the founding members of the prpl Foundation and co-chair of its Security Engineering Group. He holds a Master’s Degree in Electrical Engineering from McMaster University.
Hadi M Kamali
Postdoctoral Research Associate
University of Florida
Hadi Mardani Kamali is a postdoctoral research associate at Florida Institute for Cybersecurity Research (FICS), the Department of Electrical and Computer Engineering at the University of Florida. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at George Mason University, 2021. His research delves into hardware security with a particular focus on exploiting IP protection techniques, design-for-trust for VLSI circuits, and CAD frameworks for security (design-for-security), in which he has numerous publications in top journals and conferences including IEEE TC/TVLSI/TCAD, IACR Transactions on CHES, DAC, ICCAD, HOST, etc., with awards including nominations/selection for Best Paper Award in ISVLSI’20, ICCAD’19, ICCAD’20, IEEE CAS 2020, and HOST 2022.
Director of Application Engineering
Cadence Design Systems
Daniel Benua is an AE Director at Cadence Design Systems based in San Jose, California. Previously, Daniel was a Principal CAE at Synopsys. Dan is an industry expert in the application of formal technology to hardware design verification problems, and he has rich experiences in verification-based tool support, methodology consulting, training, and product direction.
Senior Director ASIC Business Unit
Sid Allman is a Senior Director in the ASIC Business Unit of Marvell Technology and has been working in the field of custom silicon development for over 3 decades. Sid is from Ottawa Canada and started with BNR/Nortel building their in-house silicon products. After BNR, Sid held Engineering leadership positions with LSI Logic, Cisco Systems, eSilicon, Inphi, and is now with Marvell Technology. Sid started investigating Secure Hardware while at Cisco, and is now part of the leadership team driving the Secure Development Process at Marvell.
Senior Research Scientist
Battelle Memorial Institute
Dr. Adam Kimura is a Senior Research Scientist at Battelle Memorial Institute and has been working in the field of Trusted and Assured Microelectronics since 2013. He currently serves as the technical director for Battelle’s Cyber Trust and Analytics investment R&D portfolio and is the principal investigator for Battelle’s post-silicon verification and validation research. Dr. Kimura holds his B.S, M.S., and Ph.D. in Electrical & Computer Engineering from The Ohio State University.
Adam Cron is a Distinguished Architect at Synopsys working with customers worldwide on complex Security, DFT, and ATPG issues for SoCs. He is part of the Hardware Analytics and Test R&D group, and has been with Synopsys for over 24 years. Adam is helping to automate the implementation of secure silicon as part of the DARPA AISS program. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access, editor of IEEE Std P1149.4, and is an IEEE Golden Core recipient. He also chairs a working group creating a Rest API for MITRE’s CWE and CAPEC databases.
Former VP Research Collaboration
John is a former VP Research Collaboration at Arm and has been with the company for 20 years. He has held a number of executive technology management roles in Engineering, Design Automation M&A and IT Services. Reporting to the CTO, Johns current focus is on the external research ecosystem working to both support their activities and accelerate arms technology roadmaps. John has long been a champion of Design Enablement to drive best in class integration and interoperability of arms technology and has previously served as Board Director of various Design Automation standards groups. He is currently PI for AISS a major collaborative DARPA program which addresses several aspects if rapid turnaround design and deployment methodologies for the secure SoC Device. Dr Goodenough Holds a BSc from Durham University and a PhD in VLSI Architecture from the University of Sheffield.