{"id":1660,"date":"2022-03-24T17:30:41","date_gmt":"2022-03-24T17:30:41","guid":{"rendered":"http:\/\/cad4security.org\/?page_id=1660"},"modified":"2022-12-18T18:28:57","modified_gmt":"2022-12-18T18:28:57","slug":"rtl_pat-rt-level-power-analysis-tool","status":"publish","type":"page","link":"http:\/\/cad4security.org\/index.php\/cad-tools\/side-channel-analysis\/rtl_pat-rt-level-power-analysis-tool\/","title":{"rendered":"RTL_PAT: RT-Level Power Analysis Tool"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\"><strong>Tool Name<\/strong><\/h2>\n\n\n\n<p>RTL_PAT: RT-Level Power Analysis Tool<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>CAD for<\/strong><\/h2>\n\n\n\n<p>Pre-Silicon Power Side-channel assessment<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Description<\/strong><\/h2>\n\n\n\n<p>At the RTL stage, the RTL-PAT (RTL-Power Analysis Tool) framework enables technology-independent PSC evaluation of cryptographic cores. Assessing the RTL gives designers the most freedom in immediately implementing countermeasures.<\/p>\n\n\n\n<p>RTL-PAT can also be used as a front-end sign-off framework for PSC leaks, allowing a designer to make modifications early in the design process that would be difficult or time-consuming to accomplish in subsequent design stages.<\/p>\n\n\n\n<p>RTL-PAT is also capable of analyzing FPGA, and ASIC design flows for standalone IPs and SoCs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>More Info<\/strong><\/h2>\n\n\n\n<div class=\"wp-block-buttons is-layout-flex wp-block-buttons-is-layout-flex\">\n<div class=\"wp-block-button\"><a class=\"wp-block-button__link button\" href=\"http:\/\/cad4security.org\/wp-content\/uploads\/RTL_PAT.zip\" target=\"_blank\" rel=\"noreferrer noopener\">tool link<\/a><\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Publications\/References<\/strong><\/h2>\n\n\n\n<h2 class=\"wp-block-heading\"><strong>Contacts<\/strong><\/h2>\n\n\n\n<p><a href=\"mailto:tehranipoor@ece.ufl.edu\">Mark Tehranipoor<\/a> | University of Florida<\/p>\n\n\n\n<p><a href=\"mailto:farimah@ece.ufl.edu\">Farimah Farahmandi <\/a>| University of Florida<\/p>\n\n\n\n<p><a href=\"mailto:jungminpark@ufl.edu\">Jungmin Park<\/a> | University of Florida<\/p>\n\n\n\n<p><a href=\"mailto:nitin.pundir@ufl.edu\">Nitin Pundir<\/a> | University of Florida<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Tool Name RTL_PAT: RT-Level Power Analysis Tool CAD for Pre-Silicon Power Side-channel assessment Description At the RTL stage, the RTL-PAT (RTL-Power Analysis Tool) framework enables technology-independent PSC evaluation of cryptographic cores. Assessing the RTL gives designers the most freedom in immediately implementing countermeasures. RTL-PAT can also be used as a front-end sign-off framework for PSC &hellip;<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":1602,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"acf":[],"_links":{"self":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/1660"}],"collection":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/comments?post=1660"}],"version-history":[{"count":6,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/1660\/revisions"}],"predecessor-version":[{"id":3754,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/1660\/revisions\/3754"}],"up":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/1602"}],"wp:attachment":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/media?parent=1660"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}