{"id":2535,"date":"2022-10-24T16:14:42","date_gmt":"2022-10-24T16:14:42","guid":{"rendered":"http:\/\/cad4security.org\/?page_id=2535"},"modified":"2022-10-24T16:47:38","modified_gmt":"2022-10-24T16:47:38","slug":"pre-silicon","status":"publish","type":"page","link":"http:\/\/cad4security.org\/index.php\/special-calls\/pre-silicon\/","title":{"rendered":"Pre-silicon Security Sign-off Solutions Through Design Cycle"},"content":{"rendered":"
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ACM Journal on Emerging Technologies in Computing Systems<\/strong><\/h1>\n\n\n\n

Special issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle<\/span><\/em><\/p>\n\n\n\n

Guest Editors<\/span><\/strong><\/h2>\n\n\n\n

Farimah Farahmandi<\/strong>, University of Florida, farimah@ece.ufl.edu<\/a>
Ankur Sirvastava<\/strong>, University of Maryland, ankurs@umd.edu<\/a>
Giorgio Di Natali<\/strong>, TIMA Laboratory, University of Grenoble, giorgio.di-natale@univ-grenoble-alpes.fr<\/a>
Mark Tehranipoor<\/strong>, University of Florida, tehranipoor@ece.ufl.edu<\/a><\/mark><\/p>\n\n\n\n

Security vulnerabilities in hardware designs are of major concerns since it is almost impossible to patch them once they are fabricated and deployed in the field. Recent studies have shown many vulnerabilities in SoC implementations, including side-channel leakage, information leakage, access control violations, malicious change, etc. These attacks can effectively bypass the security mechanisms built at the software level and put chips or systems at major risk. Ensuring the security of modern SoC designs is challenging due to their complexity, aggressive time-to-market demands, and the variety of attacks introduced against hardware designs. Given the wide usage of SoCs in mission-critical applications, it is critical to ensure their security before deployment. However, most of the existing solutions lack automation and rely on manual approaches and design reviews that are not efficient nor scalable. The semiconductor industry and system integrators are looking for a set of metrics, reusable security solutions, and automatic computer-aided design (CAD) tools to aid analysis, identifying, root-causing, and mitigating SoC security problems.<\/mark><\/p>\n\n\n\n

Vulnerabilities in SoCs are due to design mistakes, lack of security understanding by designers, design transformations, increased attack surfaces, and malicious intents. Further, exiting CAD tools are used in SoC design flow can introduce additional vulnerabilities in the SoCs unintentionally. For example, some design practices\/choices may make the design vulnerable to timing and power side-channel leakage. Not only will these vulnerabilities move from one level of abstraction to another, but unique vulnerabilities can also be introduced during design transformations. For example, an RTL design with power side-channel issues can suffer from access control issues when it is synthesized to gate-level, and design-for debug infrastructure will be inserted. Therefore, it is essential to have automatic CAD solutions to be able to analyze the security of SoCs in a comprehensive manner, in all levels of abstractions, and against all existing threats (e.g., fault-injection, side-channel, and hardware Trojan
attacks). CAD tools should be able to access the security of the design in the pre-silicon stage and suggest possible countermeasures while still it is possible to modify the design and address the potential vulnerabilities. Finally, addressing a security vulnerability at the later stages of the design and fabrication process would cost 10X more than the previous stage, hence it is of utmost importance to address the vulnerabilities at the higher levels of abstractions to provide higher flexibility and lower the total cost of mitigation.<\/mark><\/p>\n\n\n\n

Considering the above challenges and potential solutions, the scope of this Special Issue of ACM<\/mark> JETC calls for<\/mark> automatic CAD solutions for security sign-off in all levels of abstractions (i.e., C\/C++, RTL, gate-level, and layout) which include the following but not limited to:<\/mark><\/p>\n\n\n\n

\u2022 Power-side channel vulnerability assessment and countermeasures
\u2022 Timing-side channel vulnerability assessment and countermeasures
\u2022 Electromagnetic radiation vulnerability assessment and countermeasures
\u2022 Fault-injection vulnerability evaluation and countermeasures
\u2022 Automatic security property generation
\u2022 Security equivalence checking between different design abstractions
\u2022 Security equivalence checking between different SoCs
\u2022 Optical\/microprobing\/nanoprobing vulnerability assessment and countermeasures
\u2022 (Anti-)Reverse engineering and physical attacks
\u2022 FPGA Bitstream protection and vulnerabilities
\u2022 Trojans and backdoors: Detection and prevention
\u2022 Information leakage assessment and countermeasures
\u2022 Physical data extraction and countermeasures
\u2022 Finite statement machine hardening
\u2022 Automated physical assurance solutions<\/mark><\/p>\n\n\n\n

Submission Guidelines<\/span><\/strong><\/h2>\n\n\n\n

All original manuscripts or revisions to the ACM JETC must be submitted online at https:\/\/mc.manuscriptcentral.com\/jetc<\/a>. The author guidelines for ACM JETC can be found at <\/mark>https:\/\/dl.acm.org\/journal\/jetc\/author-guidelines<\/a><\/mark>. To make sure that your article will be considered for this special issue, you need to select the submission type as “SI: CAD for Hardware Security”. Authors must also mention the same in their submission cover letter.<\/mark><\/p>\n\n\n\n

Submitted articles must not have been previously published or currently submitted for publication elsewhere. For previously published conference papers, it is required that submissions to the special issue have at least 30% new content. Submissions that do not meet this requirement will be summarily rejected.<\/mark><\/p>\n\n\n\n

Important Dates<\/span><\/strong><\/h2>\n\n\n\n

\u2022 Submissions deadline: November 1, 2021
\u2022 First-round review decisions: January 2022
\u2022 Deadline for revision submissions: February 2022
\u2022 Notification of final decisions: April 2022
\u2022 Tentative publication: 2022<\/mark><\/p>\n\n\n\n

For further information, please contact Farimah Farahmandi at farimah@ece.ufl.edu<\/a> and Mark Tehranipoor at tehranipoor@ece.ufl.edu<\/a>.<\/mark><\/p>\n","protected":false},"excerpt":{"rendered":"

ACM Journal on Emerging Technologies in Computing Systems Special issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle Guest Editors Farimah Farahmandi, University of Florida, farimah@ece.ufl.eduAnkur Sirvastava, University of Maryland, ankurs@umd.eduGiorgio Di Natali, TIMA Laboratory, University of Grenoble, giorgio.di-natale@univ-grenoble-alpes.frMark Tehranipoor, University of Florida, tehranipoor@ece.ufl.edu Security vulnerabilities in hardware designs are of major …<\/p>\n","protected":false},"author":8,"featured_media":0,"parent":1191,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"acf":[],"_links":{"self":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/2535"}],"collection":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/users\/8"}],"replies":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/comments?post=2535"}],"version-history":[{"count":4,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/2535\/revisions"}],"predecessor-version":[{"id":2546,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/2535\/revisions\/2546"}],"up":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/1191"}],"wp:attachment":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/media?parent=2535"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}