{"id":3968,"date":"2023-01-07T18:32:28","date_gmt":"2023-01-07T18:32:28","guid":{"rendered":"http:\/\/cad4security.org\/?page_id=3968"},"modified":"2023-07-10T20:29:22","modified_gmt":"2023-07-10T20:29:22","slug":"ch10_logic_locking","status":"publish","type":"page","link":"http:\/\/cad4security.org\/index.php\/trainings\/hsl\/ch10_logic_locking\/","title":{"rendered":"Chapter 10: Logic Locking"},"content":{"rendered":"\n<h2 class=\"is-style-subheading wp-block-heading\"><strong>Chapter 10<\/strong><\/h2>\n\n\n\n<h2 class=\"is-style-subheading wp-block-heading\" style=\"font-style:normal;font-weight:100\">Logic Locking Insertion and Assessment<\/h2>\n\n\n\n<p>Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against IP theft\/piracy, tampering, counterfeiting, reverse engineering, and overproduction, and unauthorized activation. In this chapter, we demonstrate different logic locking techniques graphically in a sample circuit. In particular, this chapter can help a reader to better understand the concept of logic locking, different logic locking techniques, experimental implementation of different logic locking techniques, perform security analysis using satisfiability-based attack, and verification of the logic locked circuit with the original circuit.<\/p>\n\n\n\n<div class=\"wp-block-buttons is-layout-flex wp-block-buttons-is-layout-flex\">\n<div class=\"wp-block-button\"><a class=\"wp-block-button__link button\" href=\"http:\/\/cad4security.org\/wp-content\/uploads\/hsl\/Chapter10_Logic%20Locking.zip\">download chapter files<\/a><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p>Chapter 10 Logic Locking Insertion and Assessment Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against IP theft\/piracy, tampering, counterfeiting, reverse engineering, &hellip;<\/p>\n","protected":false},"author":6,"featured_media":2565,"parent":3964,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"_genesis_hide_title":false,"_genesis_hide_breadcrumbs":false,"_genesis_hide_singular_image":false,"_genesis_hide_footer_widgets":false,"_genesis_custom_body_class":"","_genesis_custom_post_class":"","_genesis_layout":"","footnotes":""},"acf":[],"_links":{"self":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/3968"}],"collection":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/users\/6"}],"replies":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/comments?post=3968"}],"version-history":[{"count":5,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/3968\/revisions"}],"predecessor-version":[{"id":4633,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/3968\/revisions\/4633"}],"up":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/pages\/3964"}],"wp:featuredmedia":[{"embeddable":true,"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/media\/2565"}],"wp:attachment":[{"href":"http:\/\/cad4security.org\/index.php\/wp-json\/wp\/v2\/media?parent=3968"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}