ro Project Status (12/27/2021 - 23:55:48)
Project File: RO.xise Parser Errors: No Errors
Module Name: ro Implementation State: Placed and Routed
Target Device: xc7a100t-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
5 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 0 126,800 0%  
Number of Slice LUTs 4 63,400 1%  
    Number used as logic 4 63,400 1%  
        Number using O6 output only 4      
        Number using O5 output only 0      
        Number using O5 and O6 0      
        Number used as ROM 0      
    Number used as Memory 0 19,000 0%  
    Number used exclusively as route-thrus 0      
Number of occupied Slices 2 15,850 1%  
Number of LUT Flip Flop pairs used 4      
    Number with an unused Flip Flop 4 4 100%  
    Number with an unused LUT 0 4 0%  
    Number of fully used LUT-FF pairs 0 4 0%  
    Number of slice register sites lost
        to control set restrictions
0 126,800 0%  
Number of bonded IOBs 3 210 1%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 0 32 0%  
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.50      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Dec 27 23:54:37 202101 Warning (0 new)0
Translation ReportCurrentMon Dec 27 23:54:45 2021000
Map ReportCurrentMon Dec 27 23:55:10 202104 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrentMon Dec 27 23:55:32 2021002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon Dec 27 23:55:46 2021004 Infos (0 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 12/27/2021 - 23:59:58