Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_bitgen_otherCmdLineOptions_virtex5=-g UnconstrainedPins:Allow |
PROP_intProjectCreationTimestamp=2021-12-27T09:35:40 |
PROP_intWbtProjectID=CBEBDA63161F45AA85B189BF4C9F65B2 |
PROP_intWbtProjectIteration=57 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_xilxBitgCfg_GenOpt_BinaryFile_virtex5=true |
PROP_xilxBitgCfg_GenOpt_Compress_virtex5=true |
PROP_xilxBitgCfg_GenOpt_DRC_virtex5=false |
PROP_xilxNgdbldMacro=changed |
PROP_AutoTop=true |
PROP_DevFamily=Artix7 |
PROP_DevDevice=xc7a100t |
PROP_DevFamilyPMName=artix7 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_USERDOC=1 |
FILE_VHDL=6 |