Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/vend_toplevel |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_bitgen_otherCmdLineOptions_virtex5=-g UnconstrainedPins:Allow |
PROP_intProjectCreationTimestamp=2022-01-10T23:53:51 |
PROP_intWbtProjectID=AF41B91E600648638FDF1152EEB1BBBD |
PROP_intWbtProjectIteration=24 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.vend_toplevel |
PROP_xilxNgdbldIOPads=true |
PROP_xilxNgdbldMacro=changed |
PROP_AutoTop=true |
PROP_DevFamily=Artix7 |
PROP_DevDevice=xc7a100t |
PROP_DevFamilyPMName=artix7 |
PROP_DevPackage=csg324 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=3 |
FILE_VERILOG=6 |
FILE_VHDL=2 |