vend_toplevel Project Status (01/11/2022 - 21:44:05) | |||
Project File: | topmodule.xise | Parser Errors: | No Errors |
Module Name: | rosel | Implementation State: | Programming File Not Generated |
Target Device: | xc7a100t-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Map Static Timing Report | Out of Date | Tue Jan 11 01:22:44 2022 | |
WebTalk Report | Current | Tue Jan 11 21:44:03 2022 | |
WebTalk Log File | Current | Tue Jan 11 21:44:04 2022 |