vend_toplevel Project Status (01/11/2022 - 21:44:05)
Project File: topmodule.xise Parser Errors: No Errors
Module Name: rosel Implementation State: Programming File Not Generated
Target Device: xc7a100t-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateTue Jan 11 01:22:44 2022
WebTalk ReportCurrentTue Jan 11 21:44:03 2022
WebTalk Log FileCurrentTue Jan 11 21:44:04 2022

Date Generated: 01/11/2022 - 21:44:05