vend_toplevel Project Status (01/11/2022 - 15:00:25)
Project File: topmodule.xise Parser Errors: No Errors
Module Name: vend_toplevel Implementation State: Programming File Generated
Target Device: xc7a100t-3csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
34 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 131 126,800 1%  
    Number used as Flip Flops 127      
    Number used as Latches 4      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 3,251 63,400 5%  
    Number used as logic 3,247 63,400 5%  
        Number using O6 output only 3,080      
        Number using O5 output only 30      
        Number using O5 and O6 137      
        Number used as ROM 0      
    Number used as Memory 0 19,000 0%  
    Number used exclusively as route-thrus 4      
        Number with same-slice register load 3      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 900 15,850 5%  
Number of LUT Flip Flop pairs used 3,256      
    Number with an unused Flip Flop 3,136 3,256 96%  
    Number with an unused LUT 5 3,256 1%  
    Number of fully used LUT-FF pairs 115 3,256 3%  
    Number of unique control sets 17      
    Number of slice register sites lost
        to control set restrictions
69 126,800 1%  
Number of bonded IOBs 11 210 5%  
    Number of LOCed IOBs 3 11 27%  
Number of RAMB36E1/FIFO36E1s 0 135 0%  
Number of RAMB18E1/FIFO18E1s 0 270 0%  
Number of BUFG/BUFGCTRLs 3 32 9%  
    Number used as BUFGs 3      
    Number used as BUFGCTRLs 0      
Number of IDELAYE2/IDELAYE2_FINEDELAYs 0 300 0%  
Number of ILOGICE2/ILOGICE3/ISERDESE2s 0 300 0%  
Number of ODELAYE2/ODELAYE2_FINEDELAYs 0      
Number of OLOGICE2/OLOGICE3/OSERDESE2s 0 300 0%  
Number of PHASER_IN/PHASER_IN_PHYs 0 24 0%  
Number of PHASER_OUT/PHASER_OUT_PHYs 0 24 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 96 0%  
Number of BUFRs 0 24 0%  
Number of CAPTUREs 0 1 0%  
Number of DNA_PORTs 0 1 0%  
Number of DSP48E1s 0 240 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of IBUFDS_GTE2s 0 4 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 6 0%  
Number of IN_FIFOs 0 24 0%  
Number of MMCME2_ADVs 0 6 0%  
Number of OUT_FIFOs 0 24 0%  
Number of PCIE_2_1s 0 1 0%  
Number of PHASER_REFs 0 6 0%  
Number of PHY_CONTROLs 0 6 0%  
Number of PLLE2_ADVs 0 6 0%  
Number of STARTUPs 0 1 0%  
Number of XADCs 0 1 0%  
Number of hard macros 180      
Average Fanout of Non-Clock Nets 5.54      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jan 11 21:40:36 2022013 Warnings (0 new)7 Infos (0 new)
Translation ReportCurrentTue Jan 11 21:41:01 2022001 Info (0 new)
Map ReportCurrentTue Jan 11 21:42:17 2022011 Warnings (0 new)6 Infos (0 new)
Place and Route ReportCurrentTue Jan 11 21:43:07 2022000
Power Report     
Post-PAR Static Timing ReportCurrentTue Jan 11 21:43:21 2022003 Infos (0 new)
Bitgen ReportCurrentTue Jan 11 21:44:02 2022010 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateTue Jan 11 01:22:44 2022
WebTalk ReportCurrentTue Jan 11 21:44:03 2022
WebTalk Log FileCurrentTue Jan 11 21:44:04 2022

Date Generated: 02/22/2022 - 09:35:39