Vulnerabilities in SoCs are due to design mistakes, lack of security understandings, design transformations, various attack surfaces, and malicious intents. Further, exiting CAD tools are used in SoC design flow can introduce additional vulnerabilities in the SoCs unintentionally. Not only will these vulnerabilities move from one level of abstraction to another, but unique vulnerabilities can also be introduced during design transformations. Therefore, it is essential to have automatic CAD solutions to be able to analyze the security of SoCs in a comprehensive manner, in all levels of abstractions, and against all existing threats (e.g., fault-injection, side-channel, and hardware Trojan attacks). CAD tools should be able to access the security of the design in the pre-silicon stage and suggest possible countermeasures while still it is possible to modify the design and address the potential vulnerabilities.

Considering the above challenges and potential solutions, CAD4Seccuirty workshop co-locates with ACM/IEEE DAC 2022 conference and includes experts from industry (like Synopsys, Cadence, Google, Analog Devices, Mentor Graphics, etc.), academia, and government (like DARPA, NAVY, AFRL, etc. agencies) to shed light on the need for and the recent progress on the development of automatic security CAD solutions in all levels of design abstractions. The workshop will include demos on the recent CAD for security tools to detect various vulnerabilities. There will be a panel consists of experts in the field to talk about the road map for CAD for security development. The CAD4Sec workshop will contain several technical talks on the scope of metrics and CAD as the following:

• • CAD for power-side channel vulnerability assessment
  • CAD for timing-side channel vulnerability assessment
  • CAD for electromagnetic radiation vulnerability assessment
  • CAD for fault-injection vulnerability evaluation
  • CAD for automatic security property generation
  • CAD for security equivalence checking between different design abstractions
  • CAD for security equivalence checking between different SoCs
  • CAD for Optical/microprobing/nanoprobing probing for assurance
  • CAD for (Anti-)Reverse engineering and physical attacks
  • CAD for FPGA Bitstream protection and vulnerabilities
  • CAD for Trojans and backdoors: Detection and prevention
  • CAD for physical assurance