Advanced Digital Design Project
In this course, students will learn about automated digital design. They will learn to utilize a hardware description language (HDL) in the digital design process. The language of choice is Verilog. Emphasis is on system level concepts and high-level design, and the language syntax will be presented to support the realization of the presented concepts. The students will get to design, synthesize (compile), simulate, and optimize the digital design, on a real hardware simulation platform. More specifically, a commercial computer aided design tool will be used to design a series of increasingly sophisticated designs on field programmable gate arrays (FPGAs).
Optimization and Acceleration of Deep Learning on Various Hardware Platforms
This course aims to present the mathematical, and computational challenges for holistic content/algorithm/hardware co-design of an efficient Deep Learning (DL) framework. We will discuss selected DL topics including DNNs, CNNs, GNN and Transformers in both supervised and unsupervised settings. Special emphasis will be on optimizing DL physical performance (e.g., real-time performance, energy, memory, and power) on different hardware platforms.