Tool Name
RTL_PAT: RT-Level Power Analysis Tool
CAD for
Pre-Silicon Power Side-channel assessment
Description
At the RTL stage, the RTL-PAT (RTL-Power Analysis Tool) framework enables technology-independent PSC evaluation of cryptographic cores. Assessing the RTL gives designers the most freedom in immediately implementing countermeasures.
RTL-PAT can also be used as a front-end sign-off framework for PSC leaks, allowing a designer to make modifications early in the design process that would be difficult or time-consuming to accomplish in subsequent design stages.
RTL-PAT is also capable of analyzing FPGA, and ASIC design flows for standalone IPs and SoCs.
More Info
Publications/References
Contacts
Mark Tehranipoor | University of Florida
Farimah Farahmandi | University of Florida
Jungmin Park | University of Florida
Nitin Pundir | University of Florida