The microelectronics security challenge at HOST aims to promote hardware security, provide the students with exposure to the community and prospective employers, and support interaction between academia and industry. Engineering disciplines such as Electrical and Computer Engineering and Computer Science are actively involved in ensuring the design, fabrication, and security of electronic hardware and providing a critical workforce to build and maintain the U.S. semiconductor supply chain. To promote security awareness among the students enrolled in engineering, it is essential to gain necessary hardware security skills such as a theoretical understanding of threats from untrusted semiconductor design, manufacturing, and test, and then design preventive measures to mitigate the threats. This microelectronics security challenge plans to include security assessments from intellectual properties (IP), system on a chip (SoC), and electronic supply chain.
Graduate and undergraduate students
> Step 1: Phase-1
The competition materials for different tracks will be released to all the participants. Each participating group will be required to perform the respective tasks for their tracks. The participating groups are required to prepare a detailed report.
> Step 2: Judges’ first-round review
The returned reports and codes will be evaluated by experts and go through specific criteria to determine the final candidates. The selected teams will then be invited to attend Phase-2. The students may be eligible for travel grants.
> Step 3: Phase-2
Additional tasks will be given to the selected groups at the HOST venue. Judges will test and evaluate the performance.
April 15, 2022: Phase-1 starts
May 15, 2022: Phase-1 report due
May 18, 2022: Phase-1 result
June 27, 2022: Phase-2 starts
June 28, 2022: Phase-2 ends, and winners will be declared at the social event
HOST Microelectronics Security Competition Chair: Ujjwal Guin
For more information visit: http://www.hostsymposium.org/call-for-challenge.php