Speakers

Doug Gardner, Chief Technologist – Security Center of Excellence at Analog Devices

Dougas Gardner is currently leading research and development efforts providing secure solutions for the Internet of Things, industrial control systems, high assurance control systems, end point security, and silicon. He has an extensive background in information assurance, secure communications, secure computing platforms, identity, key management, high assurance control systems, and end point security.

Norman Chang, Chief Technologist at ANSYS, Inc.

Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Chief Technologist for the Semiconductor Business Unit of ANSYS. He is also currently leading the effort of applying ML/DL at ANSYS. Prior to Apache, Dr. Chang led a group at Palo Alto HP Labs, focused on interconnect related signal/power integrity issues and contributing to the HP-Intel IA64 micro-processor design. Dr. Chang received his BS, MS, and Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 13 patents and has authored more than 50 technical papers. He also co-authored the popular book, “Interconnect Analysis and Synthesis”, published by John Wiley & Sons, 2000. Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Chief Technologist for the Semiconductor Business Unit of ANSYS. He is also currently leading the effort of applying ML/DL at ANSYS. Prior to Apache, Dr. Chang led a group at Palo Alto HP Labs, focused on interconnect related signal/power integrity issues and contributing to the HP-Intel IA64 micro-processor design. Dr. Chang received his BS, MS, and Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 13 patents and has authored more than 50 technical papers. He also co-authored the popular book, “Interconnect Analysis and Synthesis”, published by John Wiley & Sons, 2000.

Jason Oberg, Co-Founder and CTO, Tortuga Logic

Dr. Jason Oberg is a co-founder and Chief Technology Officer (CTO) of Tortuga Logic, where he is responsible for overseeing the company’s technology and strategic positioning. Dr. Oberg works closely with Tortuga Logic’s executive management team, engineering teams, and customers to drive the company’s next-generation hardware security products. Dr. Oberg brings years of deep hardware security expertise, has facilitated the development of several hardware security products, and is a member of the Common Attack Pattern Enumeration and Classification (CAPEC) and Common Weaknesses Enumeration (CWE) board. His work has been cited over 1000 times and he holds seven issued and pending patents. Prior to his CTO role, Dr. Oberg led Tortuga Logic as co-founder and CEO from 2014 – 2020 where he facilitated raising capital, recruiting the initial team, and drove the company’s product revenue growth YoY. He received his B.S. in Computer Engineering from UC Santa Barbara and an M.S. and Ph.D. in Computer Science from UC San Diego.

Saverio Fazzari, Senior Lead Engineer, Booz Allen Hamilton

Saverio Fazzari works for Booz Allen acting as a senior technical advisor to DARPA and other government agencies for numerous programs. His specialty is advanced circuit design and development strategies with a focus on hardware cyber security issues including trusted design and fabrication. Mr. Fazzari’ s experience includes extensive commercial experience, leading production innovation and development across all facets of the electronic design process. Mr. Saverio Fazzari has over 25 years of experience covering the entire electronic product development flow. He has a BSEE from Johns Hopkins, and MSEE from the University of Pittsburgh. He has published over 14 papers in industry journals and technical conferences.

Sohrab Aftabjahani, Product Security Expert/Sr. Staff Security Researcher at Intel Corporation

Sohrab Aftabjahani received his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2011. Since 2010, he has been with the Intel Corporation in Oregon contributing to its state-of-art R&D projects in various roles including senior security researcher, senior DFT engineer, senior digital design and validation engineer, and graphics Integration validation engineer. He joined Intel after 9 years of experience working as software and hardware engineer for TRW and Computer Science Corporation, Telecommunications Research Center, and several electronic system design companies. He is a senior IEEE/ACM member and serves as the chair of the IEEE Oregon section computer society and the chair of the Semiconductor Research Corporation (SRC) Trustworthy and Secure Semiconductors and Systems (T3S) Technical Advisory Board (TAB). He has served as a TAB for the SRC T3S and Computer-Aided Design and Test (CADT) since 2014. He was a 2-time recipient of the SRC Mahboob Khan outstanding liaison award in 2016 and 2019.

Mike Borza, Scientist at Synopsys

Mike Borza is a member of the technical staff for Synopsys security IP. He has more than 20 years of experience in security system engineering, and safety critical engineering before that. He is a founder and CTO of Elliptic Technologies, which was recently acquired by Synopsys. Borza has been an active contributor to the Security Task Group of IEEE 802.1; was an editor of the 802.1AR Secure Device Identifier standard; and is one of the founding members of the prpl Foundation and co-chair of its Security Engineering Group. He holds a Master’s Degree in Electrical Engineering from McMaster University.

Jay Lewis, Lead Team of Silicon Security at Microsoft

Starting Feb 2020, Jay Lewis is a member of technical lead team of silicon security project at Microsoft leading strategic projects focused on the future of the hardware supply chain, including access, assurance, and integrity. Jay was previously the Deputy Director of the Microsystems Technology Office (MTO). Since 2014, He was serving DARPA helping to set the strategic vision for the office, recruits Program Managers (PMs) who are leaders in their respective fields, and provides the oversight and guidance required to empower the PMs to drive the creation of breakthrough technology for national security. Jay received a Bachelor’s degree in Materials Science from the Georgia Institute of Technology. He received a Ph.D. in Materials Science and Engineering from the University of Florida for research on electroluminescent and photoluminescent materials and thin films for displays.

Hamid Shojaei, Senior Lead Designer of Tensor Processing Units at Google Corporation

Hamid is a senior lead designer at Google working on custom hardware for machine learning called Tensor Processing Unit or TPUs. Hamid is actively working on Google’s cloud-based static sign-off methodology that includes pre-submit with RTL Linting, Single-mode & Multimode clock domain crossing & Reset domain crossing. Hamid received his M.S. degree in Computer Engineering from the University of Tehran in Iran and Ph.D. degree in Electrical and Computer Engineering from the University of Wisconsin – Madison in 2004 and 2012, respectively.

Dan Walters, Principal Embedded Security Engineer at MITRE

Dan Walters is a Lead Digital/Micro HW Engineer at MITRE in Electronic Systems Development. Dan has worked in the area of embedded systems and security since arriving at MITRE in 2006. He helped to develop MITRE’s Secure Electronics Lab, which has advanced capabilities for researching implementation security issues such as side-channel leakage, fault induction, and trusted hardware. He is currently the principle investigator on a research project for developing tools to evaluate cryptographic software against implementation attacks.

Dan Benua, Director of Application Engineering at Cadence Design Systems

Daniel Benua is an AE Director at Cadence Design Systems based in San Jose, California. Previously, Daniel was a Principal CAE at Synopsys. Dan is an industry expert in the application of formal technology to hardware design verification problems, and he has rich expriences in verification-based tool support, methodology consulting, training, and product direction.

Adam Cron, Accomplished Design-for-Test Expert and Distinguished Architecture at Synopsys

Adam Cron is a Principal Engineer at Synopsys working with customers worldwide on complex DFT and ATPG issues for digital ICs. He is part of the Test Automation Implementation R&D Group, and has been with Synopsys for 19 years. A Syracuse University graduate, Adam has worked in test-related fields at Motorola and Texas Instruments for a total of over 32 years in the industry. Adam is Chair of the Test Technology Standards Committee overseeing the development of IEEE Test Standards. He is also Chair of IEEE Std P1838 standardizing 3D-IC testing interfaces. He chaired the IEEE Std 1149.4 Working Group from 1995 until its release. He is a member of, or has worked with, various IEEE standards’ efforts including 1149.1, 1532, 1450, 1500, 1149.8.1, 1687, etc. Adam is also an IEEE Golden Core recipient.

John Goodenough, VP Research Collaboration at ARM

John is VP Research Collaboration at Arm and has been with the company for 20 years. He has held a number of executive technology management roles in Engineering, Design Automation M&A and IT Services. Reporting to the CTO, Johns current focus is on the external research ecosystem working to both support their activities and accelerate arms technology roadmaps. John has long been a champion of Design Enablement to drive best in class integration and interoperability of arms technology and has previously served as Board Director of various Design Automation standards groups. He is currently PI for AISS a major collaborative DARPA program which addresses several aspects if rapid turnaround design and deployment methodologies for the secure SoC Device. Dr Goodenough Holds a BSc from Durham University and a PhD in VLSI Architecture from the University of Sheffield.

Matthew Areno, Senior Principal Engineer and Senior Director of Security Assurance and Cryptography at Intel Corporation

Matt is a Principal Engineer at Intel Corporation in the Intel Product Assurance and Security (IPAS) group. Dr. Areno completed his Bachelor’s and Master’s degrees at Utah State University in 2007 and took a position with Sandia National Laboratories. At Sandia, he focused on vulnerability assessment and reverse engineering of embedded systems primarily utilizing ARM-core processors. During this time, he also completed his Ph.D. at the University of New Mexico with dissertation work on strengthening embedded system security through the use of PUF-enhanced cryptographic units. In 2013, Dr. Areno took a position with Raytheon Cyber Security Innovations in Austin, TX; he served as a Chief Architect for a number of anti-tamper solutions, with specific expertise in establishing trust in COTS equipment. He joined Intel in 2019 and is now the lead of the Security Assurance and Cryptography group. Dr. Areno holds several patents and has numerous publications in the area of hardware security, system design, and PUF technologies.