• Skip to main content
  • Skip to header right navigation
  • Skip to site footer
CAD4Security

CAD4Security

CAD4Security

  • Home
  • Contests
  • Technical Events
  • Outreach
  • CAD Tools
  • SoC Vulnerability Database
  • Trainings
  • News
  • Special Calls
  • Sponsors
  • Call For Contributions

Chapter 11: Clock Glitch based Fault Injection Analysis

You are here: Home / Trainings / Hardware Security Lab (HSL) / Chapter 11: Clock Glitch based Fault Injection Analysis

Chapter 11

Clock Glitch Fault Attack on FSM in AES Controller

Secure circuits are prone to a wide range of physical attacks. Among them, fault attacks are based on modifying the circuit environment in order to change its behavior or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, clock glitch, chip underpowering, temperature increase, etc. In this chapter, we demonstrate how to perform a clock glitch in an AES block implemented on an FPGA using a ChipWhisperer CW305 target board and show how to fail an AES execution by applying clock glitches that could produce inaccurate results during the AES encryption procedure.

download chapter files

CAD4Security

Navigation

EVENTS
CAD TOOLS
SPECIAL CALLS
CONTACT US




Copyright © 2022