The emerging and ever-increasing security vulnerabilities in modern and complex hardware designs, such as SoC and complex microelectronics implementations, have been studied in recent years. Aggressive time-to-market, limited knowledge of designers in terms of security, and high cost of maintaining large team, establishing security metrics, etc have proven the need for automatic CAD solutions to aid assessment/identifying/mitigating SoC security vulnerabilities.
In consideration of the above challenges and possible solutions and continuation of the 1st (inauguration) CAD4Sec workshop, which successfully held last year at DAC’59 with more than 80 attendees, we sketch out the extension of this community-wide event by inviting the experts from the industry (e.g., Google, Microsoft, Synopsys, Cadence, ARM, Intel, etc.), academia, and government (e.g., DARPA, AFRL, NAVY, etc. agencies) to expand the knowledge, to represent the need for, and to share the recent progress on the development of automatic security CAD solutions.
The 2nd CAD4Sec workshop plan is also to extend the size and the involvement of practical demonstrations on the recent CAD for security tools by both industries/academia. There will be a panel discussion consisting of experts in the field to talk about the roadmap for CAD for security development. In continuation to the 1st CAD4Sec workshop, the 2nd CAD4Sec workshop will contain several technical talks on the scope of metrics and CAD as the following:
- CAD for Power/Timing Side Channel Assessment
- CAD for Timing Side Channel Assessment
- CAD for Fault Injection Assessment
- CAD for Electromagnetic Radiation Assessment
- CAD for Security Property Generation
- CAD for Security-oriented Equivalency Checking
- CAD for Malicious Functionality
- CAD for Security Monitoring and Validation
- CAD for Security Verification of Advanced Packaging
- CAD for Secure Heterogeneous Integration Assessment
- CAD for Physical Probing Assessment
- CAD for (Anti-)Reverse Engineering Assessment