Farinaz Koushanfar
Professor and Henry Booker Faculty Scholar
University of California, San Diego
Farinaz Koushanfar is a Professor and Henry Booker Faculty Scholar in the Department of Electrical and Computer Engineering at the University of California San Diego. She is the co-founder and co-director of Machine-Integrated Computing and Security (MICS), an upcoming UC San Diego engineering research center which focuses on technical innovation and women empowerment. She is a fellow of the Kavli frontiers of engineering of the National Academy of Engineering, and was selected to the world’s top 35 innovators under 35 (TR-35). She serves as an associate partner of the Intel Collaborative Research Institute for Secure Computing. She has received several awards and honors for her research, mentorship and teaching, including the Presidential Early Career Award for Scientists and Engineers from President Obama, the ACM SIGDA Outstanding New Faculty Award, Cisco IoT Security Grand Challenge Award, as well as Young Faculty/CAREER Awards from NSF, DARPA, ONR and ARO. She received her Ph.D. from the University of California Berkeley.
Gang Qu
Professor (and Program Director)
University of Maryland (and National Science Foundation)
Dr. Gang Qu is a professor in the Department of Electrical and Computer Engineering at the University of Maryland, College Park. He has worked extensively in the areas of hardware security and low power design. He has made a significant contribution in building the hardware security and trust community. Notably, he was an individual member of the VSIA intellectual property protection (IPP) development working group (2001) and contributed to VSIA’s IPP standards; he published the first book (2003) on hardware security, Intellectual Property Protection in VLSI Designs: Theory and Practice, based on his Ph.D. dissertation (2000); he developed a MOOC of hardware security on Coursera (2014); he co-founded the AsianHOST symposium (2016) and the IEEE CEDA hardware security and trust technique committee (HSTTC, 2020). Since October 2021, he has been working as a program director in the NSF Secure and Trustworthy Cyberspace (SaTC) program. He is a fellow of IEEE.
Doug Gardner
Chief Technologist – Security Center of Excellence
Analog Devices
Douglas Gardner is currently leading research and development efforts providing secure solutions for the Internet of Things, industrial control systems, high assurance control systems, end point security, and silicon. He has an extensive background in information assurance, secure communications, secure computing platforms, identity, key management, high assurance control systems, and end point security.
Marcus Pan
Program Manager
Semiconductor Research Corporation
Dr. Hsuanyu (Marcus) Pan joined SRC as program manager in 2021. Prior to SRC, he spent over 5 years at Boeing Research & Technology (BR&T) serving as a program manager with a focus on integrated circuits (ICs) research and development. He has successfully led research teams to execute many research programs from US government including Defense Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory (AFRL). Prior to Boeing, he was with HRL laboratories and Qualcomm as a senior design engineer to lead RF, analog and mixed-signal electronics development for commercial, automobile and aerospace wireless communication.
Rob Aitken
Technology Strategy Architect
Synopsys Inc
Rob currently is a distinguished architect in Synopsys Inc. He is an experienced technologist with broad-based expertise and connections across the semiconductor industry and associated academic ecosystem. With a detailed technical knowledge in SoC, memory and circuit design, EDA, DFT/test and reliability, Rob as an IEEE fellow has contributed to more than 50 US patents and 100+ publications. Prior to joining Synopsys, Rob was an Arm Fellow responsible for technology direction at Arm Research.
Norman Chang
Chief Technologist
ANSYS, INC
Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist of Electronics, Semiconductor, and Optics BU, ANSYS, Inc. He is also currently leading AI/ML and security initiatives at ANSYS. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds 25 patents and has co-authored over 60 technical papers and a popular book on “Interconnect Analysis and Synthesis” by Wiley-Interscience at 2000. He is in the committee of EDPS, ESDA-EDA and SI2 AI/ML SIG, and an IEEE Fellow.
Ro Cammarota
Chief Scientist of Privacy-Enhanced Computing Research
Intel Labs
Rosario Cammarota, “Ro,” is a Principal Engineer and Chief Scientist of Privacy-Enhanced Computing Research in the Emerging Security Lab at Intel Labs. He leads Privacy-Enhanced Computing Research, with a focus on the theory, application, and standardization of processing encrypted data. He received his Ph.D. in Computer Science from the University of California (Irvine) in 2013. He is a prolific author and inventor, and 50+ peer-reviewed highly cited articles, and 50+ U.S. patents. He is a Senior Member of IEEE and recipient of the SRC “Mahboob Khan” Outstanding Industry Liaison Award in 2017, 2018, and 2019.
John N. Damoulakis
Sr. Director – Advanced Technology Programs
Cadence Design Systems
Dr. John N. Damoulakis is a Sr. Director – Advanced Technology Programs at Cadence Design Systems. In that position, he focuses to bring together into an integrated framework/approach, Cadence’s core technologies on electronic design automation (EDA), simulation, emulation, and digital twinning (DT) tools to address the technology challenges encountered on information sciences, microelectronics, knowledge-based algorithms, and signal processing application domains. This involves not only the design of various domain-specific electronic components (digital, analog, photonics, etc.), but also packaging and testing, especially those involving heterogeneous functionality and materials. He holds a Ph.D. from Rice University, Houston, Texas, in ME, and a MS in EE and ME from the Technical University of Athens, Athens, Greece. Dr. Damoulakis has over 30 years of experience in concept definition, development, transition to operational systems, and management of high-technology programs for the commercial and defense industries. These activities embody not only technology development and readiness to products, but also deployment to operational systems (commercial and defense). Technologies involved include signal processing algorithms, microelectronic devices/systems design, fabrication, and testing, and real-time and non-real-time embedded processors including their applications. Dr. Damoulakis is working with numerous U.S. organizations to conceive the original and fundamental program ideas, developing and completing required constituent technologies, and transitioning the derived products to commercial and government programs. The activities involve large program efforts, as well as small efforts aiming to develop proof-of-concepts. Workforce development on microelectronics is a collateral activity to all these, which he currently pursues through the Cadence’s university program involving more than 1,000 active member universities worldwide.
Reza Azarderakhsh
CEO
PQSecure
Dr. Reza Azarderakhsh is a CEO at PQSecure as well as a professor at Florida Atlantic Universities. He received his PhD from Western University in Canada. Dr. Azarderakhsh is well-known for his contributions in applied cryptographic engineering with focus on post-quantum cryptography and secure protocol development. At PQSecure, he developed quantum-safe cryptographic IPs and is commercializing them for small embedded devices. He has published more than 100 papers in top-tier journals and conferences about cryptographic engineering and received several best paper awards from various conferences. He also serves as an associate editor at IEEE Transactions on Circuits and Systems-Cryptography Track.
Beau Bakken
Principal Engineer
Caspia Technologies
Beau Bakken is a Principal Engineer at Caspia Technologies leading projects in multiple areas of microelectronic security, including IP protection, fault injection assessment, side-channel analysis, and PCB assurance. He joined Caspia in 2020 and holds a degree in Computer Engineering from the University of Florida.
Swarup Bhunia
Semmoto Endowed Professor
University of Florida
Currently, Dr. Bhunia is a professor and Semmoto Endowed Chair in the University of Florida, FL, USA. Earlier he was appointed as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences. His research interests include hardware security and trust, adaptive nanocomputing and novel test methodologies.
Jia Di
Department Head and Professor, Rodger S. Kline Chair
University of Arkansas
Dr. Jia Di is now the Department Head and Rodger S. Kline Chair. His research area is asynchronous integrated circuit design and hardware security. His Trustable Logic Circuit Design Lab has been sponsored by various federal agencies and industry for over $23M in the past sixteen years. Dr. Di has published two books and over 120 papers on technical journals and conferences. He also has 6 U.S. patents. Dr. Di is a senior member of IEEE, an eminent member of Tau Beta Pi, and an elected member of the National Academy of Inventors.
Marilyn Wolf
Koch Professor of Engineering and Director, School of Computing
University of Nebraska-Lincoln
Dr. Wolf is Elmer E. Koch Professor of Engineering and Director of the School of Computing at the University of Nebraska-Lincoln. Prior to joining Nebraska-Lincoln, she was on the faculty of Princeton University from 1989 to 2007 and was Farmer Distinguished Chair in Embedded Computing Systems. Her research interests include cyber-physical systems, Internet-of-Things, embedded computing, embedded computer vision, and VLSI systems. She has received the IEEE Kirchmayer Graduate Teaching Award, the IEEE Computer Society Goode Memorial Award, the ASEE Terman Award, and IEEE Circuits and Systems Society Education Award. She is a Fellow of the IEEE and ACM and a Golden Core member of IEEE Computer Society. She has been elected to Phi Beta Kappa and Tau Beta Pi. She became an action figure in 2018.
Saverio Fazzari
Senior Lead Engineer
BOOZ ALLEN HAMILTON
Saverio Fazzari works for Booz Allen acting as a senior technical advisor to DARPA and other government agencies for numerous programs. His specialty is advanced circuit design and development strategies with a focus on hardware cyber security issues including trusted design and fabrication. Mr. Fazzari’ s experience includes extensive commercial experience, leading production innovation and development across all facets of the electronic design process. Mr. Saverio Fazzari has over 25 years of experience covering the entire electronic product development flow. He has a BSEE from Johns Hopkins, and MSEE from the University of Pittsburgh. He has published over 14 papers in industry journals and technical conferences.
James Wilson
Program Manager (MTO)
DARPA
Dr. James Wilson joined DARPA in July 2020 as a program manager in the Microsystems Technology Office (MTO). His research interests include the development of radio frequency (RF), analog, and digital circuits that push the power and performance envelope; novel topologies enabled through heterogeneous integration; the applications of electronics to enable new RF, EW, and communication opportunities; and hardware security. He is particularly interested in increasing the energy efficiency of electronics to enable ubiquitous, high performance systems for wideband electromagnetic spectrum operations. Prior to joining DARPA, Wilson was a team leader of the Silicon Design Team at the Army Research Laboratory (ARL).
Dipayan Saha
PhD Candidate
University of Florida
Dipayan Saha is currently pursuing a Ph.D. degree with the Department of ECE, University of Florida. His research interests include artificial intelligence (AI)-based hardware security solutions. Specifically, he is working on the development of deep learning approaches for RTL code analysis and pre-silicon side-channel leakage assessment. Dipayan earned his Bachelor of Science in Electrical and Electronics Engineering from the Bangladesh University of Engineering and Technology (BUET) in 2018. Prior to his current role at UF, Dipayan worked for both academia and industry. His research works have been published in multiple journals and conference proceedings. He has also served significant roles in different conferences and technical societies including Conference Secretary for IEEE Region 10 flagship conference IEEE TENSYMP 2020.
Rasheed Kibria
PhD Candidate
University of Florida
Rasheed Kibria obtained his BS in Electrical Engineering from the Bangladesh University of Engineering and Technology (BUET) in 2019. Currently, he is a Ph.D. student in the Electrical and Computer Engineering department at the University of Florida and working as a Research Assistant under supervision of Dr. Mark Tehranipoor. His research interest includes Hardware Security, Static Code Analysis, Secure VLSI Design, and SoC Security Verification and Validation.